US 2021/0280578 A1 · REDUCING GATE RESISTANCE IN STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

Abstract

A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

Claims20

Dependent claims

A semiconductor device structure comprising at least:

a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length;
and
a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length.

Dependencies are inferred from the claim text.

Facts

Application

17/321,563Filed 17 May 2021

Priority

26 Apr 2019

Published

9 Sep 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10D 88/01
Three-dimensional [3D] integrated devices: manufacture or treatment
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs

Reducing gate resistance in stacked vertical transport field effect transistors

Life of this patent

Reducing gate resistance in stacked vertical transport field effect transistors

Life of this patent

Abstract

Claims20