Semiconductor Device and Fabricating Method Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
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Abstract
A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
Claims20
A semiconductor device comprising:
- a FinFET component comprising a plurality of active fins;
- and
- a tuning component adjacent the FinFET component, the tuning component comprising:
- a plurality of dummy fins, wherein the plurality of dummy fins are shorter than the plurality of active fins, and wherein the plurality of dummy fins have non-uniform heights;
- and
- an isolation structure over the plurality of dummy fins.
A semiconductor device comprising:
- a FinFET component comprising:
- a plurality of active fins;
- and
- a gate stack overlapping with the plurality of active fins in a plan view;
- and
- a tuning component adjacent the FinFET component, the tuning component comprising:
- a plurality of dummy fins, wherein the plurality of dummy fins are shorter than the plurality of active fins, wherein a first dummy fin of the plurality of dummy fins has a planar top surface, and wherein a second dummy fin of the plurality of dummy fins has a concave top surface;
- and
- an isolation structure in physical contact with sidewalls and top surfaces of the plurality of dummy fins.
A semiconductor device comprising:
- a FinFET component comprising:
- a plurality of active fins;
- a first portion of an insulating layer between adjacent active fins of the plurality of active fins, top surfaces of the plurality of active fins being above a top surface of the insulating layer;
- and
- a gate stack over the insulating layer and extending along sidewalls and the top surfaces of the plurality of active fins;
- and
- a tuning component adjacent the FinFET component, the tuning component comprising:
- a plurality of dummy fins, wherein the plurality of dummy fins are shorter than the plurality of active fins, and wherein top surfaces of the plurality of dummy fins have different curvatures;
- and
- a second portion of the insulating layer covering the plurality of dummy fins.
Dependencies are inferred from the claim text.