Semiconductor module

A semiconductor module, comprising:

• a case member having a rectangular shape in a plan view of the semiconductor module, the case member having first and second side walls extending in a first direction, respectively disposed at opposite sides thereof;
• a gate terminal and a source terminal each embodied in the first side wall, and each having a flat part that is exposed from a surface of the first side wall;
• a first semiconductor element and a second semiconductor element aligned in the first direction and being electrically connected in parallel to each other, each of the first and second semiconductor elements having a gate electrode and a source electrode on an upper surface thereof;
• a gate relay layer and a source relay layer each installed between the second side wall of the case member and the first and second semiconductor elements, the gate and source relay layers being aligned in a second direction orthogonal to the first direction, positioned at a center between the first and second semiconductor elements in the first direction, and each extending in the first direction;
• a plurality of gate wires, including a first gate wire, a second gate wire and a third gate wire, wherein
• the first gate wire connects the flat part of the gate terminal to the gate relay layer by passing between the first and second semiconductor elements,
• the second gate wire connects the gate electrode of the first semiconductor element to the gate relay layer, and
• the third gate wire connects the gate electrode of the second semiconductor element to the gate relay layer;
• a plurality of source wires, including a first source wire, a second source wire and a third source wires, wherein
• the first source wire connects the flat part of the source terminal to the source relay layer by passing between the first and second semiconductor elements;
• the second source wire connects the source electrode of the first semiconductor element to the source relay layer;
• and
• the third source wire connects the source electrode of the second semiconductor element to the source relay layer, wherein
• the first source wire is located closer to the first gate wire than is any other of the plurality of gate wires, the second source wire is located closer to the second gate wire than is any other of the plurality of gate wires and the third source wire is closer to the third gate wire than is any other of the plurality of gate wires.