Stacked semiconductor device and multiple chips used therein

A combination of a plurality of chips, each of the chips is supposed to be mounted respectively on corresponding chip-mounting areas defined on a mother-substrate, the mother-substrate having a first main surface and a second main surface facing to the first main surface, and a plurality of unit elements are arranged in each of unit-element areas assigned to a first lattice defined on the first main surface, the first main surface is divided into the chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice, the mother-substrate has a plurality of substrate-side connection-elements for delivering each of signals from the plurality of the unit elements, each of the substrate-side connection-elements is assigned to a third lattice defined on the first main surface so that third lattice corresponds to an array of the unit elements, the number of chips is larger than the number of meshes of the second lattice, each of the chips comprising:

• a plurality of chip-side connection-elements feeding the signals to a circuit merged in each of the chips, arranged along the third lattice on a chip surface of each of the chips, the chip surface is facing to the first main surface,
• wherein, the mother-substrate and the plurality of the chips are provisionally jointed, and signals from the plurality of the unit elements are independently transmitted to circuits merged in the plurality of the chips to inspect normal operations of the chips,
• in a case of a defect determination such that a specific chip is determined to be defective, the specific chip is removed from the chip mounting area, and a new chip is provisionally jointed again,
• when all of the chips mounted on the mother-substrate is determined to be normal, the mother-substrate and the plurality of the chips are coupled to each other, by a non-provisional joint-process of compressing a height of the chip-side connection-element, decreasing the height lower than the value of the provisional joint-process.