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US 2021/0280530 A1Published application
Electronic package
AssigneeSiliconware Precision Industries Co., Ltd.
InventorsChi-Jen Chen, Chih-Hsun Hsu, Chee-Key Chung, Jia-Wei Pan, Chang-Fu Lin
Life of this patent
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Abstract
Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.
Claims13
An electronic package, comprising:
- a multi-chip packaging body having a plurality of electronic elements and a covering layer bonded to the plurality of electronic elements;
- and
- a stress buffer layer disposed on the multi-chip packaging body, the stress buffer layer being into contact with the plurality of electronic elements and the covering layer.
Dependencies are inferred from the claim text.