Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods

The IC package of claim I, wherein:

• the first metallization structure is disposed in a first horizontal plane;
• the second metallization structure is disposed in a second horizontal plane parallel to the first horizontal plane;
• the first IC die is disposed in a third horizontal plane parallel to the first horizontal plane;
• and
• the second die is disposed in the second horizontal plane parallel to the first horizontal plane.

The IC package of claim I, wherein:

• the first active surface of the first IC die comprises a first bottom, active surface;
• the first non-active surface of the first IC die comprises a first top, non-active surface;
• the second active surface of the second. IC die comprises a second bottom, active surface;
• and
• the second non-active surface of the second IC die comprises a second top, non-active surface.

The IC package of claim I, wherein:

• the first IC die further comprises at least one first die interconnect exposed from the first active surface;
• the second IC die further comprises at least one second die interconnect exposed from the second active surface;
• the at least one first die interconnect electrically coupled to the at least one first interconnect layer;
• and
• the at least one second die interconnect electrically coupled to the at least one second interconnect layer.

A method of fabricating an integrated circuit (IC) package, comprising:

• fabricating a first metallization structure comprising at least one first interconnect layer:
• fabricating a second metallization structure comprising at least one second interconnect layer;
• and
• fabricating an IC die module disposed between the first metallization structure and the second metallization structure, comprising:
• providing a first IC die comprising a first active surface and a first non-active surface;
• and
• providing a second IC die comprising a second active surface and a second non-active surface;
• coupling the first non-active surface of the first IC die to the second non-active surface of the second IC die to couple the first IC die to the second IC die;
• electrically coupling the first active surface of the first IC die to the at least one first interconnect layer of the first metallization structure;
• and
• electrically coupling the second active surface of the second IC die to the at least one second interconnect layer of the second metallization structure.