Hybrid selective dielectric deposition for aligned via integration

A multi-layered integrated circuit (IC), wherein at least a region of the IC comprises:

• a first dielectric material formed on a layer;
• a second dielectric material formed on the first dielectric material, the second dielectric material having a different characteristic than the first dielectric material;
• and
• conductive material formed in the first dielectric material, the second dielectric material, and the layer, the conductive material forming interconnects in the layer separated by a stack of the first dielectric material and the second dielectric material, the conductive material forming a self-aligned conductive via on one of the interconnects according to a topography of the stack, the stack of the first dielectric material and the second dielectric material electrically insulating the one of the interconnects from another one of the interconnects, a side surface of the first dielectric material being in direct contact with the self-aligned conductive via on the one of the interconnects.