Back to results
US 2021/0280459 A1Published application
Semiconductor structure with material modification and low resistance plug
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMrunal A. Khaderbad, Akira Mineji
Life of this patent
Estimating the term…
Abstract
A semiconductor device that includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a conductive feature over the semiconductor substrate and buried in the dielectric layer, and a metal plug over the conductive feature and buried in the dielectric layer, where the dielectric layer has a hydrophobic sidewall facing the metal plug.
Claims20
An integrated circuit (IC) structure, comprising:
- a semiconductor substrate (202);
- a dielectric layer (212) over the semiconductor substrate (202);
- a conductive feature (210) over the semiconductor substrate (202) and buried in the dielectric layer (212);
- and
- a metal plug (220) over the conductive feature (210) and buried in the dielectric layer (212), wherein the dielectric layer (212) has a hydrophobic sidewall (218) facing the metal plug (220).
2 more elements
An integrated circuit (IC) structure, comprising:
- a semiconductor substrate (102);
- a fin active region (fin) (108) over the semiconductor substrate (102);
- a metal gate stack (804) over and traversing the fin (108);
- a first dielectric layer (812) over the metal gate stack (804), wherein the first dielectric layer (812) has a first hydrophobic wall including and a first hydrophobic top surface (816);
- an etch stop layer (ESL) (822) over the first hydrophobic top surface (816);
- a second dielectric layer (820) over the ESL (822), the second dielectric layer (820) having a second hydrophobic wall and a second hydrophobic top surface (828);
- and
- a conductive feature (826) disposed over the metal gate stack (804), extends through the first dielectric layer (812), the first hydrophobic wall (816), the first hydrophobic top surface (816), the ESL (822), the second dielectric layer (820), the second hydrophobic wall (828) and the second hydrophobic top surface (828), wherein the second dielectric layer (820) includes a hydrophobic sidewall (828) facing the conductive feature (826).
5 more elements
An integrated circuit (IC) structure, comprising:
- a first dielectric layer (812) over a semiconductor substrate (102);
- a second dielectric layer (822) over the first dielectric layer (812);
- a third dielectric layer (820) over the second dielectric layer (822);
- a first conductive feature (804) embedded in the first dielectric layer (812),
- a second conductive feature (826) over the first conductive feature (804), wherein the second conductive feature (826) extends through the first dielectric layer (812), the second dielectric layer (822), and the third dielectric layer (820);
- and wherein the third dielectric layer (820) has a first hydrophobic sidewall (828) facing the second conductive feature (826);
- a third conductive feature (818) embedded in the first dielectric layer (812) and adjacent to the first conductive feature (804), wherein the first dielectric layer (812) includes a second hydrophobic sidewall (816) facing the third conductive feature (818);
- and
- a fourth conductive feature (824) over the third conductive feature (818) and embedded in the second dielectric layer (822) and the third dielectric layer (820), wherein the third dielectric layer includes a third hydrophobic sidewall (828) facing the fourth conductive feature (824).
6 more elements
Dependencies are inferred from the claim text.