Skip via connection between metallization levels

A semiconductor device including a skip via connection between metallization levels, comprising:

• a first conductive line having a geometry resulting from a subtractive etch process;
• a first via and a skip via disposed on the first conductive line, the first via and the first conductive line being included within a first metallization level, wherein the skip via connects a first metallization level to a third metallization level above a second metallization level;
• and
• the second metallization level including a second via on a second conductive line disposed on the first via.

A semiconductor device including a skip via connection between metallization levels, comprising:

• a first conductive line having a geometry resulting from a damascene trench formation process;
• a first via and a skip via disposed on the first conductive line, the first via and the first conductive line being included within a first metallization level, wherein the skip via connects a first metallization level to a third metallization level above a second metallization level;
• and
• the second metallization level including a second via on a second conductive line disposed on the first via.