Using a liner layer to enlarge process window for a contact via
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLi-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
Life of this patent
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLi-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
Estimating the term…
In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.
An integrated chip comprising:
An integrated chip comprising:
A method for forming an integrated chip comprising:
Dependencies are inferred from the claim text.