Redistribution Lines Having Stacking Vias
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wei Chen, Li-Hsien Huang
Life of this patent
Estimating the term…
Abstract
A method includes forming a dielectric layer over a conductive feature, forming an opening in the dielectric layer, and plating a metallic material to form a redistribution line electrically coupled to the conductive feature. The redistribution line includes a via in the opening, and a metal trace. The metal trace includes a first portion directly over the via, and a second portion misaligned with the via. A first top surface of the first portion is substantially coplanar with a second top surface of the second portion of the metal trace.
Claims20
A method comprising:
- forming a first redistribution line over and electrically coupling to a device die, wherein the first redistribution line comprises:
- a first array of vias;
- and
- a first metal trace comprising a first portion directly over and contacting the first array of vias, and a second portion vertically offset from the first array of vias;
- forming a second redistribution line, wherein the second redistribution line comprises:
- a second array of vias comprising bottom surfaces in contact with a top surface of the first metal trace, wherein each of vias in the second array of vias overlaps one of vias in the first array of vias with a one-to-one correspondence;
- and
- a second metal trace comprising a third portion directly over and contacting the second array of vias, and a fourth portion vertically offset from the second array of vias.
A method comprising:
- encapsulating a conductive post and a device die in an encapsulant;
- forming a conductive line comprising a via and a conductive trace over the via, wherein the via is over and in contact with the conductive post;
- performing a first plating process to form a first redistribution line over and electrically connected to the conductive line, the first redistribution line comprising:
- a first array of vias;
- and
- a first metal trace over and physically contacting the first array of vias;
- performing a second plating process to form a second redistribution line comprising:
- a second array of vias comprising bottom surfaces in contact with a top surface of the first metal trace, wherein each of vias in the second array of vias overlaps one of vias in the first array of vias with a one-to-one correspondence, and wherein a first via in the first array of vias and a second via in the second array of vias are vertically aligned to the conductive post;
- and
- a second metal trace comprising a third portion directly over and physically contacting the second array of vias.
A method comprising:
- encapsulating a device die and a metal post in an encapsulating material;
- forming a plurality of redistribution lines over and electrically coupling to the device die, wherein the forming the plurality of redistribution lines comprises a plurality of plating processes, and wherein upper ones of the plurality of redistribution lines overlap corresponding lower ones of the plurality of redistribution lines, and each of the plurality of redistribution lines comprises:
- an array of vias;
- and
- a metal trace over and contacting the array of vias, wherein vias in the upper ones of the plurality of redistribution lines overlap corresponding vias in the lower ones of the plurality of redistribution lines with a one-to-one correspondence.
Dependencies are inferred from the claim text.