US 2021/0280425 A1 · SEMICONDUCTOR DEVICE STRUCTURE WITH FINE PATTERNS AND METHOD FOR FORMING THE SAME

Abstract

The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

Claims20

Dependent claims

A semiconductor device structure, comprising:

a first target structure and a second target structure disposed over a semiconductor substrate;
and
a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view;
wherein the first spacer element has a rounding top surface in the cross-sectional view, and the topmost point of the first spacer element is disposed between two ends of the rounding top surface of the first spacer element.

1 more element

A method for preparing a semiconductor device structure, comprising:

forming a target material over a semiconductor substrate;
forming a plurality of energy removable patterns over the target material;
forming a plurality of spacers respectively on sidewall surfaces of the energy removable patterns;
forming a dielectric layer surrounding the plurality of energy removable patterns and the plurality of spacers;
and
etching the plurality of energy removable patterns, the dielectric layer and the target material by using the plurality of spacers as an etching mask to form a plurality of target structures;
wherein each of the plurality of spacers includes a rounding top surface in the cross-sectional view, and a topmost point of each of the plurality of spacers is disposed between two ends of the rounding top surface of each of the plurality of spacers;
wherein the topmost point of the each of the plurality of spacers is between central lines of adjacent two of the plurality of target structures in a cross-sectional view.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/810,328Filed 5 Mar 2020

Published

9 Sep 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 64/01334
Making the insulator: by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall
H10P 76/4085
Characterised by their sizes, orientations, dispositions, behaviours or shapes: characterised by the processes involved to create the masks
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 84/0147
The components including insulated gates, e.g. IGFETs: manufacturing their gate sidewall spacers

Semiconductor device structure with fine patterns and method for forming the same

Life of this patent

Semiconductor device structure with fine patterns and method for forming the same

Life of this patent

Abstract

Claims20