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US 2021/0280267 A1Published application
Configurable Soft Post-Package Repair (SPPR) Schemes
AssigneeMicron Technology, Inc.
InventorsGary Howe, John E. Riley
Life of this patent
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Abstract
Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.
Claims21
A memory device comprising:
- activation circuitry comprising a mode register bit or a control antifuse configured to send an input signal upon activation;
- and
- a logic element configured to:
- receive the input signal;
- and
- send, upon receiving the input signal, a configuration signal, wherein the configuration signal enables a multiple row repair mode.
3 more elements
A method for soft post-package repair (SPPR) comprising:
- sending, via activation circuitry, an input signal from a mode register bit or an antifuse to a logic element;
- sending, via the logic element after receiving the input signal, a configuration signal to SSPR circuitry;
- and
- enabling, via the SSPR circuitry and after receiving the configuration signal, a multiple row address repair mode.
1 more element
A memory device, comprising:
- a memory bank comprising a plurality of addressable groups of memory cells, wherein the plurality of addressable groups of memory cells comprises a primary set of addressable groups and a secondary set of addressable groups;
- and
- control circuitry configured to activate an addressable group of the plurality of addressable groups, the control circuitry comprising:
- first repair circuitry comprising a first non-volatile memory configured to store a first set of addresses corresponding to a first defective addressable group of the plurality of addressable groups repaired in a first mode;
- second repair circuitry comprising a second non-volatile memory configured to store a second set of addresses corresponding to a second defective addressable group of the plurality of addressable groups repaired in a second mode;
- activation circuitry comprising a mode register bit or a control antifuse configured to send an input signal upon activation;
- and
- a logic element configured to:
- receive the input signal;
- and
- send, upon receiving the input signal, a configuration signal, wherein the configuration signal enables a multiple row repair mode of the first defective addressable group or the second defective addressable group.
8 more elements
Dependencies are inferred from the claim text.