Semiconductor memory device
AssigneeKioxia Corporation
InventorsYasuhiro Shiino, Masahiko Iga
Life of this patent
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Abstract
A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.
Claims20
A semiconductor memory device, comprising:
- a memory block that includes a plurality of string units including memory strings comprising memory cell transistors connected in series;
- a plurality of word lines, memory cell transistors in a same row of each of the memory strings being connected to a respective word line in the plurality of word lines;
- a plurality of bit lines each respectively connected to one of the memory strings in each string unit, the plurality of bit lines being divided into a plurality of bit line groups;
- and
- a control circuit configured to perform an erasing operation on of the plurality of memory cell transistors in the memory block, wherein
- when an erase verification of the erasing operation is performed on a memory cell transistor, the control circuit is configured to execute erase verification on only a subset of memory strings in each string unit of the memory block.
A semiconductor memory device, comprising:
- a memory block that includes a plurality of string units including memory strings comprising memory cell transistors connected in series;
- a plurality of word lines, memory cell transistors in a same row of each of the memory strings being connected to a respective word line in the plurality of word lines;
- a plurality of bit lines each respectively connected to one of the memory strings in each string unit;
- and
- a control circuit configured to perform an erasing operation on of the plurality of memory cell transistors in the memory block, wherein
- when an erase verification of the erasing operation is performed on a memory cell transistor, the control circuit is configured to acquire information related to an erase speed of the memory strings of each string unit, and select the memory cell transistors of a string unit to be a verification target in the erase verification based on the acquired information on the erase speed.
A semiconductor memory device, comprising:
- a memory block that includes a plurality of string units including memory strings comprising memory cell transistors connected in series;
- a plurality of word lines, memory cell transistors in a same row of each of the memory strings being connected to a respective word line in the plurality of word lines;
- a plurality of bit lines each respectively connected to one of the memory strings, the bit lines being connected to one memory string in each string unit and being divided into a plurality of bit line groups;
- and
- a control circuit configured to perform an erasing operation on of the plurality of memory cell transistors in the memory block, wherein
- when an erase verification is performed on the memory cell transistors, the control circuit is configured to simultaneously execute the erase verification on memory cell transistors in two or more string units among the plurality of string units in the memory block.
Dependencies are inferred from the claim text.