Memory device and method of operating the memory device

A memory device comprising:

• a memory cell array comprising a plurality of planes;
• and
• a voltage generation circuit comprising a master pump component and at least one or more sub-pump components that respectively correspond to the plurality of planes,
• wherein the voltage generation circuit provides, during an interleaved operation, a plurality of output voltages that are respectively generated from the master pump component and the at least one or more sub-pump components respectively to the plurality of planes, and provides, during a non-interleaved operation, an output voltage generated from the master pump component to a selected plane of the plurality of planes.

A method of operating a memory device, the memory device including a interleaved operation and a non-interleaved operation in response to a command received,

• wherein the interleaved operation comprises:
• generating, a first output voltage and a second output voltage by activating a master pump component and a sub-pump component that respectively correspond to a first plane and a second plane;
• and
• performing overall operations of the first plane and the second plane in an interleaved manner by providing the first output voltage to the first plane and providing the second output voltage to the second plane;
• wherein the non-interleaved operation comprises:
• generating, the first output voltage by activating the master pump component;
• and
• performing an overall operation of a selected plane of the first plane and the second plane in a non-interleaved manner by providing the first output voltage to the selected plane.