US 2021/0280256 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorsKazuharu YAMABE, Yoichi MINEMURA

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Abstract

According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.

Claims20

Dependent claims

A semiconductor memory device comprising:

a first memory cell and a second memory cell capable of storing data corresponding to one of a plurality of states, and coupled to each other so as to be adjacent to each other;
a first word line coupled to a gate of the first memory cell;
a second word line coupled to a gate of the second memory cell;
and
a bit line coupled to a drain of the second memory cell, wherein
the plurality of states include:
a first state;
and
a second state adjacent to the first state and corresponding to a higher threshold voltage distribution than that of the first state, and
in a read operation of the first memory cell,
when a state of the second memory cell is the first state or one of the plurality of states corresponding to a lower threshold voltage distribution than that of the first state, data on the first memory cell is read in a first period during which a first voltage is applied to the second word line, and
when the state of the second memory cell is the second state or one of the plurality of states corresponding to a higher threshold voltage distribution than the second state, data on the first memory cell is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.

9 more elements

A semiconductor memory device comprising:

a first memory cell and a second memory cell capable of storing data corresponding to one of a plurality of states, and coupled to each other so as to be adjacent to each other;
a first word line coupled to a gate of the first memory cell;
a second word line coupled to a gate of the second memory cell;
and
a bit line coupled to a drain of the second memory cell, wherein
the plurality of states include:
a first state corresponding to a lowest threshold voltage distribution;
and
a second state adjacent to the first state and corresponding to a higher threshold voltage distribution than that of the first state;
a third state corresponding to a higher threshold voltage distribution than that of the second state;
a fourth state adjacent to the third state and corresponding to a higher threshold voltage distribution than that of the third state;
a fifth state corresponding to a higher threshold voltage distribution than that of the fourth state;
and
a sixth state adjacent to the fifth state and corresponding to a highest threshold voltage distribution that is higher than that of the fifth state, and
in a read operation of the first memory cell,
when a state of the second memory cell is the first state, data on the first memory cell is read in a first period during which a first voltage is applied to the second word line, and
when the state of the second memory cell is equal to or higher than the second state and equal to or lower than the third state, data on the first memory cell is read in a second period during which a second voltage higher than the first voltage is applied to the second word line, and
when the state of the second memory cell is equal to or higher than the fourth state and equal to or lower than the fifth state, data on the first memory cell is read in a third period during which a third voltage higher than the second voltage is applied to the second word line, and
when the state of the second memory cell is the sixth state, data on the first memory cell is read in a fourth period during which a fourth voltage higher than the third voltage is applied to the second word line.

16 more elements

A semiconductor memory device comprising:

a first memory cell and a second memory cell capable of storing data corresponding to one of a plurality of states, and coupled to each other so as to be adjacent to each other;
a first word line coupled to a gate of the first memory cell;
a second word line coupled to a gate of the second memory cell;
and
a bit line coupled to a drain of the second memory cell, wherein
the plurality of states include:
a first state;
and
a second state adjacent to the first state and corresponding to a higher threshold voltage distribution than that of the first state, and
in a read operation of the first memory cell,
when a state of the second memory cell is the first state or one of the plurality of states corresponding to a lower threshold voltage distribution than that of the first state, a first voltage is applied to the bit line when data on the first memory cell is read, and
when the state of the second memory cell is the second state or one of the plurality of states corresponding to a higher threshold voltage distribution than that of the second state, a second voltage higher than the first voltage is applied to the bit line when data on the first memory cell is read.

9 more elements

A semiconductor memory device comprising:

a first memory cell and a second memory cell capable of storing data corresponding to one of a plurality of states, and coupled to each other so as to be adjacent to each other;
a first word line coupled to a gate of the first memory cell;
a second word line coupled to a gate of the second memory cell;
and
a bit line coupled to a drain of the second memory cell, wherein
the plurality of states include:
a first state corresponding to a lowest threshold voltage distribution;
a second state adjacent to the first state and corresponding to a higher threshold voltage distribution than that of the first state;
a third state corresponding to a higher threshold voltage distribution than that of the second state;
a fourth state adjacent to the third state and corresponding to a higher threshold voltage distribution than that of the third state;
a fifth state corresponding to a higher threshold voltage distribution than that of the fourth state;
and
a sixth state adjacent to the fifth state and corresponding to a highest threshold voltage distribution that is higher than that of the fifth state, and
in a read operation of the first memory cell,
when a state of the second memory cell is the first state, a first voltage is applied to the bit line, and
when the state of the second memory cell is equal to or higher than the second state and equal to or lower than the third state, a second voltage higher than the first voltage is applied to the bit line,
when the state of the second memory cell is equal to or higher than the fourth state and equal to or lower than the fifth state, a third voltage higher than the second voltage is applied to the bit line, and
when the state of the second memory cell is the sixth state, a fourth voltage higher than the third voltage is applied to the bit line.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/993,509Filed 14 Aug 2020
Priority: JP 2020-0377605 Mar 2020
Published: 9 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 11/5671
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge trapping in…

Family

US 11,264,105 B2Related patent
US 2021/0280256 A1This patent

From the US filing history. Foreign family members aren’t listed.

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