Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power

A method of operating an analog neural memory system comprising a first array comprising non-volatile memory cells arranged in rows and columns, a second array comprising non-volatile memory cells arranged in rows and columns, column multiplexors, local bit lines, and global bit lines, the method comprising:

• selecting, by the column multiplexors, a local bit line of the first array or a local bit line of the second array, and coupling the selected bit line to a global bit line;
• and
• multiplexing the global bit line with a second global bit line adjacent to the global bit line.

A method of operating an analog neural memory system comprising an array of non-volatile memory cells, the method comprising:

• receiving, by a first n-bit analog-to-digital converter, a first output from the array;
• receiving, by a second n-bit analog-to-digital converter, a second output from the array;
• combining the first n-bit analog-to-digital converter with the second n-bit analog-to-digital converter to form a third analog-to-digital converter that generates a third output based on the first output and the second output, wherein the third output has a precision greater than n bits.

An analog neural memory system comprising:

• an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a dummy bit line in a plurality of dummy bitlines.

An analog neural memory system comprising:

• an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a bit line in a plurality of bitlines, and weights of a neural network are distributed among the bitlines to maintain voltage drop or power consumption at a substantially equal level among the bitlines.