Back to results
US 2021/0280238 A1Published application
Semiconductor memory device
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsTsuyoshi Midorikawa, Toshiaki Dozaka
Life of this patent
Estimating the term…
Abstract
According to one embodiment, there is provided a semiconductor memory device including a bit cell, a pair of bit lines and an assist circuit. The pair of bit lines are electrically connected to the bit cell. The assist circuit is configured to be connected to the bit lines and including one or more capacitive elements. A ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.
Claims20
A semiconductor memory device comprising:
- a bit cell;
- a pair of bit lines electrically connected to the bit cell;
- and
- an assist circuit configured to be connected to the bit lines and including one or more capacitive elements,
- wherein a ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.
2 more elements
Dependencies are inferred from the claim text.