Double-Pitch-Layout Techniques And Apparatus Thereof

An apparatus, comprising:

• a substrate;
• and
• a memory circuit on the substrate, the memory circuit comprising an array of memory cells, control circuits, a word-line driver, and a plurality of input/output (I/O) circuits, the plurality of I/O circuits comprising a plurality of I/O pins comprising at least a first group of I/O pins and a second group of I/O pins, wherein:
• an M×N array of one-bit memory cells of the array of memory cells are grouped into N/2 two-column pairs of M×1 one-bit memory cells with respective I/O circuits of the plurality of I/O circuits, with M being a positive integer representative of a number of rows and N being a positive integer representative of a number of columns,
• each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells and a second column of M×1 one-bit memory cells,
• a layout of the first column of M×1 one-bit memory cells and a layout of the second column of M×1 one-bit memory cells are mirrored in horizontal and vertical axes such that the first group of I/O pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of the layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array
• wherein the memory circuit further comprises an internal power mesh, and wherein a pitch of the internal power mesh is different from a pitch of corresponding I/O pins of each of the one-bit memory cells.