Memory device receiving data clock signals and operation method thereof

An operation method of a memory device, the operation method comprising:

• receiving a dynamic data clock command to cause a data clock receiving circuit to be in an enabled state until a predetermined particular command is received;
• enabling the data clock receiving circuit in response to the dynamic data clock command;
• receiving the predetermined particular command;
• and
• disabling the data clock receiving circuit in response to the predetermined particular command.

A memory device comprising:

• a plurality of memory ranks comprising a first memory rank and a second memory rank;
• a first pin through which a data clock signal is input from outside of the memory device;
• a data clock receiving circuit configured to receive the data clock signal input via the first pin;
• a second pin through which a command is input from outside of the memory device;
• and
• a control logic configured to control a data operation of the memory device based on the command input via the second pin, enable the data clock receiving circuit based on a first command input via the second pin, control data operations of the first memory rank and the second memory rank during an interval when the data clock receiving circuit is in an enabled state, and disable the data clock receiving circuit based on a second command input via the second pin,
• wherein the first command is a command that causes the data clock receiving circuit, after the data clock receiving circuit is enabled, to be maintained in an enabled state until the second command is input via the second pin.