Memory device

A memory device, comprising:

• a plurality of first memory cells, each of the plurality of first memory cells including:
• a first gate structure embedded in a substrate,
• a first active region adjacent to the first gate structure and having a first channel region,
• a first gate insulating layer between the first gate structure and the first channel region, and
• a capacitor connected to the first active region and extended in a direction perpendicular to a top surface of the substrate;
• a plurality of second memory cells, each of the plurality of second memory cells including:
• a second gate structure,
• a second active region adjacent to the second gate structure and having a second channel region, and
• a second gate insulating layer between the second gate structure and the second channel region, the second gate insulating layer including a ferroelectric material having a higher dielectric constant than the first gate insulating layer,
• wherein the plurality of second memory cells are to store or erase data based on a polarization state of the second gate insulating layer;
• and
• a plurality of transfer switches, each of the plurality of transfer switches including active regions connected to the first gate structure and the second gate structure.

A memory device, comprising:

• a first memory cell array including first memory cells having volatility;
• a second memory cell array including second memory cells having non-volatility, each of the second memory cells having a size smaller than a size of each of the first memory cells;
• transfer switches between the first memory cells and the second memory cells;
• and
• a controller configured to turn on the transfer switches, read data of at least one of the first memory cells, and store the data in at least one of the second memory cells.