Memory component with adjustable core-to-interface data rate ratio

A method of operation in a memory component, the method comprising:

• receiving a request to read data from a memory bank within the memory component;
• dividing the data from the memory bank into a plurality of portions;
• and
• transferring the plurality of portions from the memory bank to a data interface block within the memory component over a plurality of communication buses, wherein each portion of the plurality of portions is transferred in a separate operation associated with a different one of the plurality of communication buses, and wherein each operation is separated in time by a delay period.

A memory component comprising:

• a memory bank;
• a data interface block configured to transfer data between the memory component and a component external to the memory component;
• a plurality of communication buses coupled between the memory bank and the data interface block;
• and
• bus routing circuitry coupled to the data interface block and the memory bank, wherein the bus routing circuitry is configured to:
• divide data from the memory bank into a plurality of portions;
• and
• transfer the plurality of portions from the memory bank to a data interface block within the memory component over the plurality of communication buses, wherein each portion of the plurality of portions is transferred in a separate operation associated with a different one of the plurality of communication buses, and wherein each operation is separated in time by a delay period.

A system comprising a memory component, the memory component comprising:

• a plurality of memory banks, wherein each of the plurality of memory banks comprises a plurality of storage cells;
• a data interface block to transfer data between the memory component and an external component in the system;
• and
• a plurality of communication buses coupled between each memory bank of the plurality of memory banks and the data interface block, wherein the plurality of communication buses is configured to transfer a plurality of portions of data from one of the plurality of memory banks to the data interface block, wherein each portion of the plurality of portions is transferred in a separate operation associated with a different one of the plurality of communication buses, and wherein each operation is separated in time by a delay period.