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US 2021/0280147 A1Published application
Goa circuit and display device
AssigneeTcl China Star Optoelectronics Technology Co., Ltd.
InventorsSuping XI, Tianhong WANG
Life of this patent
Estimating the term…
Abstract
A GOA circuit and a display panel are provided. In the GOA circuit, a first clock signal, a second clock signal, and a nth stage clock signal are separated into an input terminal of a first unit and an input terminal of a second unit. This reduces time that a thin film transistor in an inverter is subjected to forward current stress, thereby reducing offset of a threshold voltage of the thin film transistor, improving stability of the thin film transistor, and ensuring a normal output of a scan signal waveform.
Claims20
A gate driver on array (GOA) circuit, comprising:
- a plurality of cascaded GOA circuit units, wherein a nth stage GOA circuit unit comprises a pull-down maintenance circuit module, a power supply low-voltage signal terminal, and a first node, where n is greater than 4 and n is a positive integer, the pull-down maintenance circuit module comprises:
- an inverter comprising a first unit, a second unit, and a first thin film transistor, wherein the first unit and the second unit comprise a plurality of thin film transistors, a gate of the first thin film transistor is connected to the first node, a first terminal of the first thin film transistor is connected to the power supply low-voltage signal terminal, a second terminal of the first thin film transistor, the first unit, and the second unit are connected to a second node, an input terminal of the first unit is connected to a first clock signal and a nth stage clock signal, and an input terminal of the second unit is connected to a second clock signal and the nth stage clock signal;
- and
- a voltage stabilizing unit connected to the first node, the power supply low-voltage signal terminal, and the second node, wherein the inverter uses a potential of the first node as an input signal and uses a potential of the second node as an output signal to control the voltage stabilizing unit to stabilize the potential of the first node.
1 more element
A display panel, comprising:
- a plurality of rows of pixels and a GOA circuit, the GOA circuit comprising a plurality of cascaded GOA circuit units, wherein each row of the pixels is connected to a corresponding GOA circuit unit in the GOA circuit and is driven by the GOA circuit unit, a nth stage GOA circuit unit comprises a pull-down maintenance circuit module, a power supply low-voltage signal terminal, and a first node, where n is greater than 4 and n is a positive integer, the pull-down maintenance circuit module comprises:
- an inverter comprising a first unit, a second unit, and a first thin film transistor, wherein the first unit and the second unit comprise a plurality of thin film transistors, a gate of the first thin film transistor is connected to the first node, a first terminal of the first thin film transistor is connected to the power supply low-voltage signal terminal, a second terminal of the first thin film transistor, the first unit, and the second unit are connected to a second node, an input terminal of the first unit is connected to a first clock signal and a nth stage clock signal, and an input terminal of the second unit is connected to a second clock signal and the nth stage clock signal;
- and
- a voltage stabilizing unit connected to the first node, the power supply low-voltage signal terminal, and the second node, wherein the inverter uses a potential of the first node as an input signal and uses a potential of the second node as an output signal to control the voltage stabilizing unit to stabilize the potential of the first node.
1 more element
A display panel, comprising:
- a plurality of rows of pixels and a GOA circuit, the GOA circuit comprising a plurality of cascaded GOA circuit units, wherein each row of the pixels is connected to a corresponding GOA circuit unit in the GOA circuit and is driven by the GOA circuit unit, a nth stage GOA circuit unit comprises a pull-down maintenance circuit module, a power supply low-voltage signal terminal, and a first node, where n is greater than 4 and n is a positive integer, the pull-down maintenance circuit module comprises:
- an inverter comprising a first unit, a second unit, and a first thin film transistor, the first unit comprises a second thin film transistor and a third thin film transistor, the second unit comprises a fourth thin film transistor and a fifth thin film transistor, a gate of the first thin film transistor is connected to the first node, a first terminal of the first thin film transistor is connected to the power supply low-voltage signal terminal, a gate of the second thin film transistor is connected to the first clock signal having a phase opposite to a phase of the first clock signal, a first terminal of the second thin film transistor, a first terminal of the third thin film transistor, a first terminal of the fourth thin film transistor, and a first terminal of the fifth thin film transistor are connected to the nth stage clock signal, and a second terminal of the third thin film transistor, a second terminal of the fifth thin film transistor, and a second terminal of the first thin film transistor are connected to the second node;
- and
- a voltage stabilizing unit connected to the first node, the power supply low-voltage signal terminal, and the second node, wherein the inverter uses a potential of the first node as an input signal and uses a potential of the second node as an output signal to control the voltage stabilizing unit to stabilize the potential of the first node.
1 more element
Dependencies are inferred from the claim text.