Dynamic variable bit width neural processor

A method for operating a neural processor, the method comprising:

• generating, by a first multiply circuit of a neural engine circuit operating a first mode, first output data of a first bit width by multiplying the first input data to a first kernel coefficient;
• generating, by a second multiply circuit of the neural engine circuit operating in the first mode, second output data of the first bit width by multiplying the second input data to a second kernel coefficient;
• and
• by the first circuit and the second circuit operating as a part of a combined computation circuit, third output data of a second bit width by multiplying the third input data with a third kernel coefficient.

An electronic device, comprising:

• a memory storing a first set of instructions associated with a machine learning model;
• a neural processor, comprising:
• a buffer circuit configured to store input data associated with the machine learning model;
• and
• a neural engine circuit coupled to the buffer circuit, the neural engine circuit comprising a first multiply circuit and a second multiply circuit, and the neural engine circuit configured to:
• receive, in a first mode, first input data and second input data from the buffer circuit,
• generate, in the first mode using the first multiply circuit, first output data of a first bit width by multiplying the first input data to a first kernel coefficient,
• generate, in the first mode using the second multiply circuit, second output data of the first bit width by multiplying the second input data to a second kernel coefficient,
• receive, in the second mode, third input data from the buffer circuit, and
• operate, in the second mode, the first multiply circuit with at least the second multiply circuit as a combined computation circuit to generate third output data of the second bit width by multiplying the third input data to a third kernel coefficient.