US 2021/0279197 A1Published application

Circuits and methods for enabling redundancy in an electronic system employing cold-sparing

AssigneeTallannQuest LLC DBA Apogee Semiconductor

InventorsMark Hamlyn, David A. Grant

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Abstract

CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Claims18

Dependent claims

A cold-sparable low-leakage output stage for a metal-oxide semiconductor IC, the IC having a first I/O pad, a positive supply terminal at potential VDD, and a ground terminal at a ground potential VSS, the output stage comprising:

a low-side branch comprising a first NMOS transistor having a source connected to the ground terminal, a drain connected to the first I/O pad, and a gate driven by an NMOS drive path;
and
a high-side branch comprising
a first pair of back-to-back PMOS transistors consisting of a first PMOS transistor having a drain connected to the first I/O pad, a gate driven by a PMOS drive path, and a source of the first PMOS transistor connected to a source of a second PMOS transistor, a drain of the second PMOS transistor being connected to the positive supply terminal,
a second NMOS transistor having a source connected to the ground terminal, a drain connected to a gate of the second PMOS transistor, and a gate driven by an ENABLE_CLAMP_BAR signal held high during normal powered operation and brought low during cold-sparing,
and a second pair of back-to-back PMOS transistors consisting of a third PMOS transistor and a fourth PMOS transistor, the third PMOS transistor having a drain connected to the first I/O pad, a gate driven by the ENABLE_CLAMP_BAR signal, and a source, the source of the third PMOS transistor being connected to a source of a fourth PMOS transistor, a drain of the fourth PMOS transistor being connected to the gate of the second PMOS transistor and to the drain of the second NMOS transistor, and a gate of the fourth PMOS transistor also driven by the ENABLE_CLAMP_BAR signal,
whereby when the circuit is cold-spared with VDD at ground potential, the first pair of back-to-back PMOS transistors blocks a leakage path from the first I/O pad to the unpowered positive supply terminal, and the second pair of back-to-back PMOS transistors blocks a leakage path from the first I/O pad through the second NMOS transistor to the ground terminal.

4 more elements

A cold-sparable charged-device model (CDM) electrostatic discharge protection circuit for a metal-oxide semiconductor IC, the IC having a positive supply terminal at potential VDD, a ground terminal at a ground potential VSS, and a substrate at potential VSS, the protection circuit comprising:

an input connected to an I/O pad of the IC;
an output connected to an input of the IC;
a first NMOS transistor having a first source, a first drain, a first gate, and a first body connection, wherein the source and gate are both connected to the ground terminal, the first body connection is connected to the substrate, and the first drain is connected to the output;
a second NMOS transistor having a second source, a second drain, a second gate, and a second body connection, wherein the second source and second gate are connected to the output, and the second body connection is connected to the substrate;
a current-limiting series resistor RCDC having a first end and a second end, the first end being connected to the input, and the second end being connected to the output;
and
a third NMOS transistor having a third source, a third drain, a third gate, and a third body connection, wherein the third source is connected to the second drain, the third gate and third drain are connected to the positive supply terminal, and the third body connection is connected to the substrate,
whereby the third transistor blocks a leakage path from the output to the positive supply terminal when the circuit is cold-spared with VDD at ground potential.

5 more elements

A cold-sparable majority-voting output circuit for a metal-oxide semiconductor IC having an I/O pad and a ground terminal, the majority-voting output circuit comprising:

a first, a second, and a third independent functional circuit, each functional circuit having an input and an output, and each functional circuit configured so as to produce a substantially identical output logic signal as the other functional circuits in response to an identical stimulus at its respective input;
and
a first, a second, and a third cold-sparable low-leakage output stage, each output stage having an input and an output, wherein the output of the first functional circuit is connected to the input of the first output stage, the output of the second functional circuit is connected to the input of the second output stage, and the output of the third functional circuit is connected to the input of the third output stage, and the outputs of the first, second, and third output stages are all connected together and to the I/O pad to produce a single common output level at the I/O pad,
whereby in the presence of a single-event effect or other transient or permanent malfunction that affects any one of the first, second, or third functional circuits or first, second, or third output stages, thereby causing the output logic signal of the affected circuit to differ from the output logic signals of the other two functional circuits, a voltage sum of the output logic signals at the I/O pad from the first, second, and third cold-sparable output stages will result in a common output logic level at the I/O pad representing the identical output logic signals from the other two functional circuits.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/194,221Filed 6 Mar 2021
Priority: 6 Mar 2020
Published: 9 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 13/4072
Electrical coupling: drivers or receivers
H03K 19/00315
Modifications for increasing the reliability for protection: in field-effect transistor circuits
H03K 19/0136
In bipolar transistor circuits: by means of a pull-up or down element
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS

Family

Application62/986,610Us provisional application · filed 6 Mar 2020
US 11,726,943 B2Related patent
US 2021/0279197 A1This patent

From the US filing history. Foreign family members aren’t listed.

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