Protocol including a command-specified timing reference signal

A memory controller to a control a memory device, the memory controller comprising:

• circuitry to identify an event where the memory device has not transferred data for a least a predetermined idle period;
• circuitry to cause, in response to the event, the memory device to commence outputting of a specified timing reference signal prior to transfer of data following passage of the predetermined idle period;
• circuitry to calibrate a value of a timing parameter in the memory controller using the specified timing reference signal;
• and
• circuitry to receive the data transferred from the memory device following passage of the predetermined idle period in dependence on the calibrated value of the timing parameter.

A memory controller to a control a memory device, wherein the memory controller is to couple to the memory device via a command path, a data path and an error detection information transmission path, the memory controller comprising:

• circuitry to identify an event where the memory device has not transferred data for a least a predetermined idle period;
• circuitry to cause, in response to the event, the memory device to commence outputting of a specified timing reference signal via the error detection information transmission path prior to transfer of the data by the memory device to the memory controller following passage of the predetermined idle period, wherein the specified timing reference signal comprises a toggling pattern;
• circuitry to calibrate a value of a timing parameter in the memory controller using the specified timing reference signal;
• and
• circuitry to receive the transfer of the data from the memory device using circuitry dependent to sample the data path according to timing dependent on the calibrated value of the timing parameter.

A method of operating a memory controller, the memory controller to a control a memory device, the method comprising, with circuitry of the memory controller:

• identifying an event where memory device has not transferred data for a least a predetermined idle period;
• causing, in response to the event, the memory device to commence outputting of a specified timing reference signal prior to transfer of data following passage of the predetermined idle period;
• calibrating a value of a timing parameter in the memory controller using the specified timing reference signal;
• and
• receiving the data transferred from the memory device following passage of the predetermined idle period in dependence on the calibrated value of the timing parameter.