Address obfuscation for memory
AssigneeMicron Technology, Inc.
InventorsDonald M. Morgan, Sean S. Eilert, Bryce D. Cook
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.
Claims20
A method, comprising:
- selecting, for use throughout a first time interval, a first mapping function for a first memory array of a memory device and a second mapping function for a second memory array of the memory device, the second mapping function different from the first mapping function, the first mapping function and the second mapping function configured to map logical addresses to physical addresses for the first memory array and the second memory array respectively;
- receiving, during the first time interval, a first access command associated with a first logical address for first data stored in the first memory array;
- using the first mapping function, based at least in part on the first data associated with the first logical address being stored in the first memory array, to determine a first physical address within the first memory array, the first physical address corresponding to the first logical address;
- and
- accessing the first data stored in the first memory array based at least in part on the first physical address.
An apparatus, comprising:
- an interface configured to receive logical addresses for accessing data stored in a first memory array and a second memory array;
- a selection component coupled with the interface and configured to select, for use throughout a first time interval, a first mapping function for the first memory array and a second mapping function for the second memory array, the second mapping function different from the first mapping function, the first mapping function and the second mapping function configured to map logical addresses to physical addresses for the first memory array and the second memory array respectively;
- and
- a mapping component coupled with the selection component and configured to map logical addresses received via the interface for the first memory array during the first time interval to physical addresses within the first memory array based at least in part on the first mapping function, the mapping component further configured to map logical addresses received via the interface for the second memory array during the first time interval to physical addresses within the second memory array based at least in part on the second mapping function.
An apparatus, comprising:
- an interface configured to receive logical addresses for a plurality of memory dice;
- and
- a selection component configured to select, for use throughout a first time interval, a first mapping function for a first memory array of a first memory dice of the plurality of memory dice and a second mapping function for a second memory array of a second memory dice of the plurality of memory dice, the second mapping function different from the first mapping function, the first mapping function and the second mapping function configured to map logical addresses to physical addresses for the first memory array and the second memory array respectively.
Dependencies are inferred from the claim text.