Repair circuit and memory device including the same

A memory device, comprising:

• a memory cell array including a plurality of memory cells coupled between a plurality of word lines and bit lines;
• a plurality of storage circuits each suitable for storing a repair address of the memory cells and storing valid information representing whether the repair address is stored or not in the corresponding storage circuit;
• and
• a plurality of enable signal generation circuits respectively corresponding to the storage circuits and each suitable for generating an enable signal representing whether a corresponding storage circuit is operable or not,
• wherein each of the enable signal generation circuits generates a valid signal for the corresponding storage circuit based on valid information of the corresponding storage circuit and an enable signal representing whether at least one storage circuit other than the corresponding storage circuit, among the storage circuits, is operable or not.

A circuitry comprising:

• 1st to Nth storage circuits configured to respectively store repair addresses from most recent to least recent, each storage circuit further storing validity information and failure information;
• 1st to Nth enable signal circuits respectively corresponding to the 1st to Nth storage circuits and each configured to generate a validity signal and an enable signal;
• a determination circuit configured to sequentially determine, based on the validity signal and the failure information, whether the respective repair addresses are available;
• a control circuit configured to compare, for a repair operation, a row address sequentially with the respective repair addresses that are determined to be available,
• wherein each enable circuit generates:
• the validity signal based on a corresponding validity information and the enable signal generated by a subsequent enable circuit, and
• the enable signal based on the validity signal and a corresponding failure information.