Storage apparatus and memory device control method

A storage apparatus, comprising:

• an interface unit configured to include one or more interfaces connected to a plurality of nonvolatile semiconductor memory devices which are a plurality of devices having a plurality of nonvolatile semiconductor memories;
• a storage unit configured to include one or more memories;
• and
• a processor unit configured to include one or more processors connected to the interface unit and the storage unit, wherein the processor unit releases a low power consumption state of a first nonvolatile semiconductor memory device at a timing according to a lapsed time after the first nonvolatile semiconductor memory device in the low power consumption state in which the error check processing and the refresh processing are not performed is in the low power consumption state and an estimated ambient temperature of the first nonvolatile semiconductor memory device at the lapsed time,
• the error check processing is processing of checking the number of errors which is the number of errors in data read from a first area in a nonvolatile semiconductor memory in the first nonvolatile semiconductor memory device,
• the refresh processing is processing of moving error-corrected data to a second area in the nonvolatile semiconductor memory in the first nonvolatile semiconductor memory device when the number of errors specified in the error check processing is equal to or greater than a predetermined number,
• the first nonvolatile semiconductor memory device is any of the plurality of nonvolatile semiconductor memory devices, and
• the first nonvolatile semiconductor memory device executes the error check processing and the refresh processing when the low power consumption state is released.