Memory device and test operation thereof
AssigneeSK hynix Inc.
InventorsSeong Ju LEE, Joon Hong PARK, Young Mok JEONG
Life of this patent
Estimating the term…
Abstract
A memory device includes a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result, a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit, and an output data alignment circuit suitable for converting the read path data into serial data to output the serial data as output data.
Claims22
A memory device, comprising:
- a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result;
- a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit;
- and
- an output data alignment circuit suitable for converting the read path data into serial data and outputting the serial data as output data.
A method for operating a memory device, comprising:
- converting parallel read data that are read from a plurality of memory cells into serial data to be provided to an input/output pad, converting the serial data feeding back from the input/output pad back into parallel data, and writing the parallel data as write data in the memory cells;
- comparing the read data and the written data with each other to determine whether a first comparison result is a pass or a failure;
- and
- converting test data into the serial data instead of the read data and comparing the test data and the parallel data with each other to determine whether a second comparison result is a pass or a failure, when the first comparison result is determined as the failure.
A method for operating a memory device, comprising:
- feeding back read data that are read in parallel from a plurality of memory cells through an input/output pad and converting the fed-back data into parallel data;
- and
- comparing the parallel data with each other to determine whether a comparison result is a pass or a failure.
A memory device comprising:
- a memory core configured to store write data and provide read data;
- a path selector configured to provide test data;
- a first loop-back path configured to loop the test data, which is transferred from the path selector to an input/output (IO) pad, back to the path selector as first looped-back data;
- a second loop-back path configured to loop the read data, which is transferred from the memory core to the path selector, back to the memory core as second looped-back data;
- and
- a first detector configured to detect a defect of a path between the path selector and the IO pad by comparing the test data with the first looped-back data and to detect a defect of a path between the memory core and the path selector by comparing the read data with the second looped-back data.
Dependencies are inferred from the claim text.