Lifetime telemetry on memory error statistics to improve memory failure analysis and prevention

A compute platform, comprising:

• a processor;
• a plurality of Dual Inline Memory Modules (DIMMs), each comprising a plurality of Dynamic Random Access Memory (DRAM) devices comprising memory and including a plurality of banks of memory cells organized in arrays comprising row-wise wordlines and column-wise bitlines;
• a memory controller coupled to the plurality of DIMMs and used to access the memory, the memory controller integrated on the processor or coupled to the processor and enabled to detect correctable errors and uncorrectable errors;
• and
• embedded logic to:
• monitor memory error information corresponding to at least one of detected correctable errors and uncorrectable memory errors, the memory error information for a given correctable or uncorrectable memory error identifying an associated DRAM device;
• decode corresponding micro-level error bits information from the memory error information and generate Micro-level Error Statistic Indicators (MESIs);
• and
• cause information associated with the MESIs generated for DRAM devices on a given DIMM to be written to persistent storage on that DIMM.

A method implemented in a computing platform comprising platform hardware including a plurality of Dynamic Random Access Memory (DRAM) devices on one of more Dual Inline Memory Modules (DIMMs) comprising:

• monitoring memory error information corresponding to at least one of detected correctable errors and uncorrectable memory errors, the memory error information for a given correctable or uncorrectable memory error identifying an associated DRAM device in an associated DIMM;
• decoding corresponding micro-level error bits information from the memory error information and generating Micro-level Error Statistic Indicators (MESIs);
• and
• causing information associated with the MESIs generated for DRAM devices on a given DIMM to be written to persistent storage on that DIMM.