Back to results
US 2021/0279074 A1Published application
Overflow detection and correction in state machine engines
AssigneeMicron Technology, Inc.
InventorBrian Lewis Brown
Life of this patent
Estimating the term…
Abstract
State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
Claims20
An apparatus, comprising:
- a primary chip configured to initiate a write operation at a first clock rate;
- and
- a secondary chip coupled to the primary chip and configured to receive data from the primary chip at the first clock rate as part of the write operation, wherein the primary chip comprises a bus control system configured to receive an indication of an amount of data locations being utilized in a storage location of the primary chip and transmit a halt signal configured to halt the write operation based, at least in part, on the amount of data locations being utilized in the storage location.
An apparatus, comprising:
- a primary chip comprising a storage location, wherein the primary chip is configured to initiate a write operation at a first clock rate;
- and
- a secondary chip coupled to the primary chip and configured to receive data from the primary chip at the first clock rate as part of the write operation, wherein the primary chip comprises a bus control system configured to:
- receive an indication of an amount of data locations being utilized in the storage location;
- determine if any of the data locations in the storage location are available;
- transmit an indication to allow writing of additional data to the available data locations at the first write clock speed prior to halting the write operation when the bus control system determines that the available data locations are available;
- and
- transmit a transmit a halt signal configured to halt the write operation when the available data locations have been filled.
5 more elements
A method, comprising:
- initiating a write operation by a primary chip;
- transmitting data from the primary chip to a secondary chip as part of the write operation;
- determining an overflow indication as in an indication of an amount of data locations being utilized in a storage location of the primary chip;
- and
- transmitting a halt signal configured to halt the write operation based, at least in part, on the amount of data locations being utilized in the storage location.
2 more elements
Dependencies are inferred from the claim text.