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US 2021/0279055 A1Published application
Technique for performing bit-linear transformations
AssigneeNVIDIA Corporation
InventorsNirmal Saxena, Ming Yiu Siu, Justin Paul Luitjens
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and techniques to perform bit matrix multiply and accumulate operations. In at least one embodiment, a Galois residue is determined in response to performing a bit matrix multiply and accumulate operation.
Claims25
A processor comprising:
- one or more circuits to perform one or more operations to calculate a Galois residue value in response to performing a bit matrix multiply and accumulate (BMMA) operation.
A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:
- perform one or more operations to calculate a Galois residue value in response to performing a bit matrix multiply and accumulate (BMMA) operation.
A method comprising:
- receiving an instruction for a bit matrix multiply and accumulate (BMMA) operation;
- and
- executing, by a processor, the BMMA operation to generate one or more elements of a result matrix at an output of a datapath, wherein each element of the one or more elements of the result matrix is generated, at least in part, by calculating a bitwise logical AND operation and applying an XOR operation to at least a portion of a result of the bitwise AND operation.
A system comprising:
- one or more processors to generate an encoded output set of bits that represents a low density parity check (LDPC) encoded set of data based, at least in part, on an input set of bits, in response to performing one or more sets of bit matrix multiply and accumulate (BMMA) operations in parallel, wherein one or more of the one or more sets of BMMA operations include a first subset of BMMA operations performed with respect to a first set of data that represents bits of a payload block of a parity check matrix, and a second set of data that represents a portion of a parity encoding matrix, and a second subset of BMMA operations that calculates a parity value for a parity encoding matrix row based at least in part on one or more results of the first subset of BMMA operations;
- and
- one or more memories to store the encoded output set of bits.
Dependencies are inferred from the claim text.