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US 2021/0279039 A1Published application
Time-shared compute-in-memory bitcell
AssigneeQUALCOMM Incorporated
InventorAnkit SRIVASTAVA
Life of this patent
Estimating the term…
Abstract
A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.
Claims24
A compute-in-memory bitcell array, comprising:
- a read bit line;
- a shared capacitor having a first plate connected to the read bit line;
- a first compute-in-memory bitcell that includes a first pair of cross-coupled inverters having a first output node for a first stored bit and includes a first transmission gate connected between the first output node and a second plate of the shared capacitor, the first transmission gate being configured to close in response to a first input bit being true and to open in response to the first input bit being false;
- and
- a second compute-in-memory bitcell that includes a second pair of cross-coupled inverters having a second output node for a second stored bit and includes a second transmission gate connected between the second output node and the second plate of the shared capacitor, the second transmission gate being configured to close in response to a second input bit being true and to open in response to the second input bit being false.
2 more elements
A compute-in-memory method, comprising:
- in a first bitcell, controlling a first pair of transmission gates to drive a second plate of a shared capacitor with a first multiplication signal responsive to a first multiplication of a first input bit with a first stored bit, the shared capacitor having a first plate connected to a read bit line;
- sampling a first charge of the read bit line while grounding the second plate of the shared capacitor after the first multiplication to provide a first sampled charge of the read bit line;
- in a second bitcell, controlling a second pair of transmission gates to drive the second plate of the shared capacitor with a second multiplication signal responsive to a second multiplication of a second input bit with a second stored bit;
- and
- sampling a second charge of the read bit line while grounding the second plate of the shared capacitor after the second multiplication to provide a second sampled charge of the read bit line.
2 more elements
A compute-in-memory array, comprising:
- a read bit line;
- a first shared capacitor having a first plate connected to the read bit line;
- a second shared capacitor having a first plate connected to the read bit line;
- a first set of compute-in-memory bitcells, each compute-in-memory bitcell in the first set of compute-in-memory bitcells having a first capacitor node connected to a second plate of the first shared capacitor;
- and
- a second set of compute-in-memory bitcells, each compute-in-memory bitcell in the second set of compute-in-memory bitcells having a second capacitor node connected to a second plate of the second shared capacitor.
3 more elements
Dependencies are inferred from the claim text.