Coherency locking schemes

A system, comprising:

• a plurality of memory components;
• and
• a processing device operatively coupled with the plurality of memory components, the processing device to:
• receive a first write command from a device that is external to the system, the first write command to write a first block of data at a first memory address of the plurality of memory components;
• lock a first coherency of the first memory address responsive to receiving the first write command;
• receive a second write command from a sub-component of the system, the second write command to write a second block of data at a second memory address of the plurality of memory components;
• and
• maintain a second coherency of the second memory address in an unlocked state after receiving the second write command.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

• receive a first write command from an external device to write a first block of data at a first memory address of a memory device;
• lock a first coherency of the first memory address responsive to receiving the first write command;
• and
• receive a second write command from an internal component of the processing device to write a second block of data at a second memory address of the memory device, wherein a second coherency of the second memory address remains in an unlocked state after receiving the second write command.