Methods of forming a v-groove for a fiber optics cable on an integrated photonics chip

A device, comprising:

• a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a base semiconductor layer, a buried insulation layer positioned above the base semiconductor layer and an active semiconductor layer positioned above the buried insulation layer;
• a V-groove in the base semiconductor layer, the V-groove being adapted to have a fiber optics cable positioned therein;
• an optical component positioned above the V-groove and above the buried insulation layer;
• a first layer of silicon dioxide comprising USG (undoped silicate glass) silicon dioxide positioned above the optical component, wherein the first layer of silicon dioxide has a thickness of about 110 nm;
• a second layer of silicon dioxide comprising TEOS (tetraethoxysilane) silicon dioxide positioned on and in contact with the first layer of silicon dioxide, wherein the second layer of silicon dioxide has a thickness of about 240 nm;
• and
• a third layer of silicon dioxide comprising TEOS (tetraethoxysilane) silicon dioxide positioned on and in contact with the second layer of silicon dioxide.

A method, comprising:

• forming a CMOS-based integrated circuit above a semiconductor-on-insulator (SOI) substrate in a CMOS region and forming an optical component above the SOI substrate in a photonics region;
• forming a first layer of silicon dioxide above the SOI substrate in both the CMOS region and the photonics region, the first layer of silicon dioxide being positioned above the optical component;
• forming a first layer of silicon nitride above the first layer of silicon dioxide in both the CMOS region and the photonics region;
• forming a second layer of silicon nitride in the CMOS region and above the first layer of silicon nitride in the photonics region;
• removing the first and second layers of silicon nitride from the photonics region;
• forming a second layer of silicon dioxide in both the CMOS region and the photonics region;
• forming a third layer of silicon dioxide above the second layer of silicon dioxide in both the CMOS region and the photonics region;
• forming BEOL (back-end-of-line) layers of insulating material and etch-stop layers in both the CMOS region and the photonics region;
• performing an etching process to remove the BEOL layers of insulating material and etch-stop layers from above the photonics region while leaving the BEOL layers of insulating material and etch-stop layers in position in the CMOS region, wherein the etching process stops on or within the second or third layers of silicon dioxide;
• and
• forming a fourth layer of silicon dioxide in the photonics region.