Software and firmware support for device interface board configured to allow devices supporting multiple different standards to interface with the same socket

A non-transitory computer-readable medium having computer-readable program code embodied therein for causing a computer system to perform a method for testing DUTs, the method comprising

• receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT);
• generating commands and data for testing the DUT;
• routing signals associated with the commands and the data in the FPGA, wherein signals are routed based on a first set of pin assignments for a first DUT type and signals are routed based on a second set of pin assignments for a second DUT type, and wherein further the FPGA is selectable for routing signals between the first and second DUT type;
• and
• transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on a type of the DUT, and wherein the first and second sets of pin assignments are different.

A system for performing a method for testing DUTs, the system comprising:

• a processing device communicatively coupled with a memory and configured to:
• receive instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT);
• generate commands and data for testing the DUT;
• route signals associated with the commands and the data in the FPGA based on a type of the DUT, wherein signals are routed based on a first set of pin assignments for a first DUT type and signals are routed based on a second set of pin assignments for a second DUT type, and wherein further the FPGA is selectable for routing signals between the first and second DUT type;
• and
• transmit the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT, and wherein the first and second sets of pin assignments are different.