Two-stage ramp adc in crossbar array circuits for high-speed matrix multiplication computing

A crossbar array circuit comprising:

• one or more bit lines;
• one or more word lines;
• one or more 1T1R cells connected between the bit lines and the word lines;
• one or more DACs connected to the one or more word lines;
• one or more access controls connected to the one or more 1T1R cells and configured to select a 1T1R cell in the one or more 1T1R cells and to program the selected 1T1R cell;
• and
• one or more two-stage ramp ADCs connected to the one or more bit lines, wherein one of the two-stage ramp ADCs comprises:
• a transimpedance amplifier configured to convert an input signal from current to voltage;
• a comparator connected to the transimpedance amplifier;
• a switch bias set connected to the comparator;
• a switch side capacitor in parallel with the switch bias set;
• a ramp side capacitor in parallel with the switch bias set;
• a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal;
• a counter;
• and
• a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.