Transistors with Different Threshold Voltages

A method comprising:

• providing a workpiece comprising a substrate, first vertically stacked channel members in a first area of the substrate, second vertically stacked channel members in a second area of the substrate, and third vertically stacked channel members in a third area of the substrate;
• depositing a gate dielectric layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• depositing a sacrificial layer over the gate dielectric layer;
• etching the sacrificial layer such that a portion of the sacrificial layer remains disposed between adjacent ones of the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• selectively removing all of the sacrificial layer in the second area;
• depositing a first work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• selectively removing the first work function layer and the sacrificial layer in the first area;
• depositing a second work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members, the second work function layer being different from the first work function layer;
• and
• depositing a passivation layer over the second work function layer.

A method comprising:

• providing a workpiece comprising a substrate, first vertically stacked channel members in a first area of the substrate, second vertically stacked channel members in a second area of the substrate, and third vertically stacked channel members in a third area of the substrate;
• depositing a gate dielectric layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• depositing a sacrificial layer over the gate dielectric layer;
• partially and selectively etching the sacrificial layer such that a portion of the sacrificial layer is disposed between adjacent ones of the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• selectively removing all of the sacrificial layer in the second area;
• depositing a first work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• selectively removing the first work function layer and the sacrificial layer in the first area,
• depositing a second work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members, the second work function layer being different from the first work function layer;
• depositing a passivation layer over the second work function layer;
• selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third area;
• selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third area;
• depositing a glue layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;
• and
• depositing a metal fill layer over the glue layer,
• wherein the first work function layer is different from the second work function layer,
• wherein a composition of the first work function layer is substantially identical to a composition of the glue layer.

A method comprising:

• forming a first plurality of channel members, a second plurality of channel members, and a third plurality of channel members over a substrate;
• depositing a gate dielectric layer over and around each of the first plurality of channel members, each of the second plurality of channel members, and each of the third plurality of channel members;
• after the depositing of the gate dielectric layer, forming a first work function layer around each of the second plurality of channel members;
• after the selectively forming of the first work function layer, forming a second work function layer around each of the first plurality of channel members and each of the second plurality of channel members;
• depositing a passivation layer over the first plurality of channel members, the second plurality of channel members, and the third plurality of channel members;
• selectively removing the first work function layer, the second work function layer, and the passivation layer over the third plurality of channel members to expose the gate dielectric layer around each of the third plurality of channel members;
• and
• depositing a glue layer over the first plurality of channel members, the second plurality of channel members, and the third plurality of channel members.