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US 2021/0265370 A1Published application
Methods and apparatuses with vertical strings of memory cells and support circuitry
AssigneeMicron Technology, Inc.
InventorsTakehiro Hasegawa, Koji Sakui
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.
Claims19
(canceled)
A memory structure, comprising:
- a memory array formed on a first surface of a substrate;
- support circuitry formed on a second surface of the substrate, the second surface of the substrate opposite the first surface of the substrate, the support circuitry comprising multiple transistors;
- and
- first and second substrate transistors formed in the substrate in association with a respective opening in the substrate, the first and second substrate transistors respectively including,
- a gate insulator lining the opening and defining a central insulator opening;
- a conductive material extending within the opening and within the insulator and forming a gate;
- a first annular diffusion region extending around the opening at the first surface of the substrate;
- a second annular diffusion region extending around the opening at the second surface of the substrate;
- and
- a shallow trench insulation (STI) region separating the first annular diffusion regions of the first and second substrate transistors from one another at the first surface of the substrate.
7 more elements
A memory apparatus, comprising:
- a memory array formed on a first surface of a substrate;
- support circuitry formed on a second surface of the substrate, the second surface of the substrate opposite the first surface of the substrate, the support circuitry comprising a surround gate transistor (SGT) in association with a respective opening in the substrate, the SGT comprising:
- one or more substrate openings in the substrate and containing an insulator material;
- a diffusion region in the substrate and isolated by the insulator material, wherein the diffusion region is doped to form a first polarity semiconductor gate material of the SGT;
- an opening in the gate material lined with a dielectric, forming a dielectric opening, and
- a semiconductor channel material extending within the dielectric opening, the semiconductor channel material doped to form an opposite polarity semiconductor from the gate material, wherein opposite ends of the semiconductor channel material form source/drain regions of the SGT.
3 more elements
A memory structure, comprising:
- a memory array formed over a first surface of a substrate;
- support circuitry formed over a second surface of the substrate, the second surface of the substrate opposite the first surface of the substrate;
- multiple substrate transistors formed in the substrate in association with respective openings in the substrate, the substrate transistors respectively including,
- a conductive material extending within an opening in the substrate and defining an annular opening around the conductive material;
- a gate insulator lining the annular opening and a conductive gate material extending within the opening and over the gate insulator to form a gate;
- a first annular diffusion region extending around the opening at the first surface of the substrate to form a drain of the substrate transistor, the first annular diffusion region separated by a dielectric from the gate material;
- and
- a second diffusion region beneath the conductive material, and separated from the gate material by the gate insulator, the second diffusion region forming a source of the substrate transistor.
5 more elements
A memory structure, comprising:
- a memory array formed over a first surface of a substrate;
- support circuitry formed over a second surface of the substrate, the second surface of the substrate opposite the first surface of the substrate;
- and
- multiple substrate transistors formed in the substrate in association with respective openings in the substrate, the substrate transistors respectively including,
- an annular control gate material extending within an annular opening in the substrate, the annular control gate material isolated from the substrate by a dielectric within the annular opening;
- a first diffusion region in the substrate within a center region of the annular control gate material, the first diffusion region doped to an opposite polarity from the substrate to form a source region of the substrate transistor at the first surface of the substrate;
- and
- a second annular diffusion region extending around the annular control gate material, the second annular diffusion region isolated from the control gate material by a dielectric, the second annular diffusion region doped to an opposite polarity from the substrate to form a drain region of the substrate transistor at the first surface of the substrate.
5 more elements
Dependencies are inferred from the claim text.