Stacked Nanosheet CFET with Gate All Around Structure

A method of forming a complementary field effect transistor (CFET) device, the method comprising the steps of:

• forming at least one nanosheet device stack on a substrate comprising alternating first nanosheets of a first material and second nanosheets of a second material, wherein lower nanosheets in the at least one nanosheet device stack are separated from the substrate and from upper nanosheets in the at least one nanosheet device stack by sacrificial nanosheets;
• forming a zeta (ζ)-shaped dielectric spacer separating the lower nanosheets from the upper nanosheets;
• forming lower source and drains on opposite sides of the lower nanosheets and upper source and drains on opposite sides of the upper nanosheets, separated from the lower source and drains by an isolation spacer;
• selectively removing the first nanosheets, forming gaps in the lower nanosheets and the upper nanosheets;
• and
• forming a first gate in the gaps surrounding a portion of each of the lower nanosheets in a gate-all-around configuration comprising at least one first workfunction-setting metal, and a second gate in the gaps surrounding a portion of each of the upper nanosheets in a gate-all-around configuration comprising at least one second workfunction-setting metal, wherein the at least one first workfunction-setting metal is separated from the at least one second workfunction-setting metal by the ζ-shaped dielectric spacer.