FETS and Methods of Forming FETS

A semiconductor device comprising:

• a first fin extending from a raised portion of a substrate;
• a second fin extending from the raised portion of the substrate, the second fin being adjacent the first fin;
• a first isolation region on a first top surface of the raised portion of the substrate and between the first fin and the second fin;
• a second isolation region along opposing sidewalls of the raised portion of the substrate;
• an epitaxial region over the first fin and the second fin, the epitaxial region extending over the first isolation region, wherein the epitaxial region comprises:
• a semiconductor layer on the first fin and the second fin, the semiconductor layer having a first dopant concentration;
• a stressor layer on the semiconductor layer, the stressor layer having a second dopant concentration, the second dopant concentration being larger than the first dopant concentration;
• and
• a capping layer on the stressor layer, the capping layer having a third dopant concentration, the third dopant concentration being less than the second dopant concentration;
• a gate structure along sidewalls and over upper surfaces of the first fin and the second fin;
• and
• a void interposed between the epitaxial region and the first isolation region.

A semiconductor device comprising:

• a first fin and a second fin extending from a raised portion of a substrate, the first fin and the second fin comprising a first semiconductor material;
• an isolation region along opposing sidewalls of the raised portion of the substrate and over the raised portion between the first fin and the second fin;
• a gate structure along sidewalls and over upper surfaces of the first fin and the second fin;
• a source/drain region over the first fin and the second fin, the source/drain region comprising a second semiconductor material, the second semiconductor material being different than the first semiconductor material, the second semiconductor material of the source/drain region extending continuously from the first fin to the second fin;
• a semiconductor capping layer over the source/drain region, wherein a dopant concentration of the semiconductor capping layer is less than a dopant concentration of the source/drain regions;
• a void above the raised portion of the substrate, the void being interposed between the source/drain region and the isolation region, wherein the void exposes a surface of the first semiconductor material and a surface of the second semiconductor material;
• and
• a dielectric layer interposed between the void and the isolation region, the dielectric layer completely covering an upper surface of the isolation region between the first fin and the second fin.