Method and system for replacement of memory cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHiroki NOGUCHI
Life of this patent
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Abstract
A memory system is disclosed. The memory system includes a first memory array, an error correction code circuit, and a monitor circuit. The error correction code circuit is configured to receive data from the first memory array to correct, at least one error bit in the received data. The error correction code circuit is further configured to generate an error determination signal. The monitor circuit is coupled to the error correction code circuit. The monitor circuit is configured to receive the error determination signal and record at least one fail word address associated with the at least one error bit and corresponding failure times in an error table.
Claims20
A memory system, comprising:
- a first memory array;
- an error correction code circuit configured to receive data from the first memory array to correct at least one error bit in the received data, and configured to generate an error determination signal;
- and
- a monitor circuit coupled to the error correction code circuit, wherein the monitor circuit is configured to receive the error determination signal and record at least one fail word address associated with the at least one error bit and corresponding failure times in an error table.
A method, comprising:
- detecting, by an error correction code circuit, error bits of a plurality of sequences of data received from a memory array;
- incrementing, by a monitor circuit, a plurality of counter values in an error table, wherein the plurality of counter values are associated with a plurality of fail word addresses corresponding to the plurality of sequences of data;
- determining, by the monitor circuit, whether the plurality of counter values are greater than a threshold value;
- and
- in response to the determining, replacing, by a replace circuit, a plurality memory locations corresponding to the plurality of fail word addresses with a plurality of backup memory locations.
A method, comprising:
- counting, by a monitor circuit, a plurality of counter values associated with a plurality of fail word addresses, wherein the plurality of fail word addresses are associated with error bits of data received from a plurality of memory cells;
- updating, by the monitor circuit, a repair information with a first word address of the plurality of fail word addresses, wherein the first word address corresponds to a maximal one of the plurality of counter values;
- and
- replacing, by a replace circuit, the plurality of memory cells with a plurality of backup memory cells corresponding to the first word address before the plurality of memory cells are not able to be repaired.
Dependencies are inferred from the claim text.