Wear leveling for random access and ferroelectric memory

A method, comprising:

• deactivating a first row of memory cells of a first section of a memory array based at least in part on holding a set of data in a first set of latches associated with a wear-leveling operation;
• sending the set of data to a second set of latches based at least in part on the wear-leveling operation, wherein the second set of latches is associated with a second section of the memory array;
• and
• pre-charging a second row of memory cells of the second section with the set of data in the second set of latches based at least in part on sending the set of data to the second set of latches.

A memory device, comprising:

• a memory array comprising a plurality of sections of ferroelectric memory cells, each section of the plurality of sections associated with a set of sense components and a set of latches;
• and
• a controller coupled with one or more of the memory array, the set of sense components, and the set of latches, wherein the controller is operable to:
• deactivate a first row of memory cells of a first section of the memory array based at least in part on holding a set of data in a first set of latches associated with a wear-leveling operation;
• send the set of data to a second set of latches based at least in part on the wear-leveling operation, wherein the second set of latches is associated with a second section of the memory array;
• and
• pre-charge a second row of memory cells of the second section with the set of data in the second set of latches based at least in part on sending the set of data to the second set of latches.

A method, comprising:

• deactivating a first row of memory cells of a memory array while holding a set of data in a first set of latches associated with a wear-leveling operation;
• pre-writing, after isolating memory cells of a second row of memory cells of the memory array, the second row of memory cells with a logic state based at least in part on the wear-leveling operation and on deactivating one or more isolation devices associated with the second row of memory cells;
• transmitting the set of data from the first set of latches to a second set of latches associated with the second row of memory cells;
• closing the first set of latches based at least in part on the transmitting;
• and
• pre-charging the second row of memory cells with the set of data using the second set of latches based at least in part on pre-writing the second row of memory cells with the logic state and on closing the first set of latches.