Display panel driver, source driver, and display device including the source driver

A source driver, comprising:

• a decoder to which a digital signal including a plurality of bits is input, the plurality of bits including a most significant bit (MSB) and a first non-MSB;
• and
• a level shifter including a first input terminal, a first output terminal via which a first signal input to the first input terminal is output, a second input terminal, and a second output terminal via which a second signal input to the second input terminal is output,
• wherein
• the decoder includes a first port to which the MSB is input, a second port to which an inverted MSB is input, a third port to which the first non-MSB is input, and a fourth port to which an inverted first non-MSB is input,
• the MSB is provided to the first port via the second input and output terminals of the level shifter,
• the inverted MSB is provided to the second port via the first input and output terminals of the level shifter,
• the first non-MSB is provided to the third port via the first input and output terminals of the level shifter, and
• the inverted first non-MSB is provided to the fourth port via the second input and output terminals of the level shifter.

A display device, comprising:

• a display panel including a plurality of pixels;
• a plurality of gate lines electrically connected to the pixels;
• a gate driver that provides a plurality of gate voltage signals to the pixels via the gate lines;
• a plurality of source lines electrically connected to the pixels;
• a source driver that provides a plurality of driving voltages to the pixels via the source lines;
• and
• a timing controller that provides a plurality of control signals to the source driver and the gate driver,
• wherein the source driver comprises:
• a shift register that receives the control signals and a digital signal including a plurality of bits, and that outputs the digital signal in accordance with the control signals,
• wherein the plurality of bits includes a most significant bit (MSB) and a first non-MSB;
• and
• a plurality of level shifters including a first level shifter provided with the MSB, and a second level shifter provided with the first non-MSB,
• wherein
• the first level shifter includes a first input terminal, a first output terminal via which a first signal input to the first input terminal is output, a second input terminal, and a second output terminal via which a second signal input to the second input terminal is output,
• the second level shifter includes a third input terminal, a third output terminal via which a third signal input to the third input terminal is output, a fourth input terminal, and a fourth output terminal via which a fourth signal input to the fourth input terminal is output,
• an inverted MSB is input to the first input terminal of the first level shifter,
• the MSB is input to the second input terminal of the first level shifter,
• the first non-MSB is input to the third input terminal of the second level shifter, and
• an inverted first non-MSB is input to the fourth input terminal of the second level shifter.