Loading apparatus and method for convolution with stride or dilation of 2

A graphics processing unit (GPU), comprising:

• a general purpose register (GPR) comprising registers;
• an arithmetic logic unit (ALU) configured to read pixels of an image independently of a shared memory;
• a level 1 (L1) cache coupled to the GPR and configured to store the pixels read by the ALU;
• and
• wherein the ALU is configured to implement a pixel mapping that maps the pixels read from the L1 cache to the registers of the GPR, wherein implementing the pixel mapping comprises:
• fetching a quad of pixels from the L1 cache, wherein the quad includes pixels of first, second, third, and fourth pixel types based on a position in the quad;
• grouping the pixels of the first, second, third, and fourth pixel types respectively into four groups, wherein the four groups comprising a first group that includes a first set of pixels of a first pixel type, a second group that includes a second set of pixels of a second pixel type, a third group that includes a third set of pixels of a third pixel type, and a fourth group that includes a fourth set of pixels of a fourth pixel type;
• and
• for each of the four groups, separating the pixels included in the group into three regions, the three regions for each group comprising a first region having a fifth set of pixels, a second region having a sixth set of pixels, and a third region having a seventh set of pixels.