Leakage analysis on semiconductor device

A method, comprising:

• calculating expected boundary leakages of a semiconductor device;
• and
• adjusting a layout of the semiconductor device based on at least the expected boundary leakages;
• wherein calculating the expected boundary leakages of the semiconductor device comprises:
• detecting boundaries between abutted cells in the layout of the semiconductor device;
• identifying attributes associated with cell edges of the abutted cells, wherein the attributes include at least one of terminal types of the cell edges;
• identifying cell abutment cases based on the attributes associated with the cell edges, wherein the cell abutment case is associated with the terminal types;
• and
• calculating maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases.

A method, comprising:

• storing at least one leakage lookup table related to leakage current values for cell abutment cases that are different from each other, wherein the cell abutment cases are associated with terminal types of abutted cells in a semiconductor device;
• identifying the cell abutment cases based on attributes that are associated with the terminal types;
• calculating maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases;
• calculating boundary leakages between the abutted cells based on the maximal boundary leakages;
• and
• adjusting a layout of the semiconductor device based on the boundary leakages.