US 2021/0264082 A1Published application

Hardware deprocessing using voltage imaging for hardware assurance

AssigneeUniversity of Florida Research Foundation, Inc.

InventorsMark M. Tehranipoor, Navid Asadi-Zanjani, Olivia Pauline Paradis, Nitin Varshney

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Abstract

Embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities for setting deprocessing parameters used in conducting hardware deprocessing on a hardware. In accordance with one embodiment, a method is provided that includes: receiving sample images using different E-beam voltages, wherein each image is captured from a backside of the hardware using a different E-beam voltage; generating thickness-based contour maps, wherein each map is generated for an image and includes contour lines indicating locations having a same thickness of remaining material; generating estimated E-beam penetration depths, wherein each depth is generated for an image and is based at least in part on the E-beam voltage used to capture the image; generating an estimated thickness measurement of the remaining material based at least in part on the contour maps and the penetration depths; and setting the deprocessing parameters based at least in part on the estimated thickness measurement.

Claims20

Dependent claims

A method for setting one or more deprocessing parameters used in conducting hardware deprocessing on a hardware, the method comprising:

receiving, via one or more processors, a set of sample images using a plurality of electron beam (E-beam) voltages for the hardware, wherein each sample image of the set of sample images is captured from a backside of the hardware using an E-beam voltage of the plurality of E-beam voltages;
generating, via the one or more processors, a set of thickness-based contour maps, wherein each thickness-based contour map of the set of thickness-based contour maps is generated for a sample image of the set of sample images and comprises one or more contour lines indicating locations on the backside of the hardware having a same thickness of remaining material;
generating, via the one or more processors, a set of estimated E-beam penetration depths, wherein each estimated E-beam penetration depth of the set of estimated E-beam penetration depths is generated for a sample image of the set of sample images and is based at least in part on the E-beam voltage used to capture the sample image;
generating, via the one or more processors, an estimated thickness measurement of the remaining material for the backside of the hardware based at least in part on the set of thickness-based contour maps and the set of estimated E-beam penetration depths;
and
setting, via the one or more processors, the one or more deprocessing parameters based at least in part on the estimated thickness measurement.

3 more elements

An apparatus for setting one or more deprocessing parameters used in conducting hardware deprocessing on a hardware, the apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to at least:

receive a set of sample images using a plurality of electron beam (E-beam) voltages for the hardware, wherein each sample image of the set of sample images is captured from a backside of the hardware using an E-beam voltage of the plurality of E-beam voltages;
generate a set of thickness-based contour maps, wherein each thickness-based contour map of the set of thickness-based contour maps is generated for a sample image of the set of sample images and comprises one or more contour lines indicating locations on the backside of the hardware having a same thickness of remaining material;
generate a set of estimated E-beam penetration depths, wherein each estimated E-beam penetration depth of the set of estimated E-beam penetration depths is generated for a sample image of the set of sample images and is based at least in part on the E-beam voltage used to capture the sample image;
generate an estimated thickness measurement of the remaining material for the backside of the hardware based at least in part on the set of thickness-based contour maps and the set of estimated E-beam penetration depths;
and
set the one or more deprocessing parameters based at least in part on the estimated thickness measurement.

3 more elements

A non-transitory computer storage medium comprising instructions for setting one or more deprocessing parameters used in conducting hardware deprocessing on a hardware, the instructions being configured to cause one or more computer processors to at least perform operations configured to:

receive a set of sample images using a plurality of electron beam (E-beam) voltages for the hardware, wherein each sample image of the set of sample images is captured from a backside of the hardware using an E-beam voltage of the plurality of E-beam voltages;
generate a set of thickness-based contour maps, wherein each thickness-based contour map of the set of thickness-based contour maps is generated for a sample image of the set of sample images and comprises one or more contour lines indicating locations on the backside of the hardware having a same thickness of remaining material;
generate a set of estimated E-beam penetration depths, wherein each estimated E-beam penetration depth of the set of estimated E-beam penetration depths is generated for a sample image of the set of sample images and is based at least in part on the E-beam voltage used to capture the sample image;
generate an estimated thickness measurement of the remaining material for the backside of the hardware based at least in part on the set of thickness-based contour maps and the set of estimated E-beam penetration depths;
and
set the one or more deprocessing parameters based at least in part on the estimated thickness measurement.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/167,381Filed 4 Feb 2021
Priority: 20 Feb 2020
Published: 26 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 30/323
Circuit design at the digital level: translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist…
G06F 30/20
Computer-aided design [CAD]: design optimisation, verification or simulation
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Family

Application62/979,031Us provisional application · filed 20 Feb 2020
US 11,604,912 B2Related patent
US 2021/0264082 A1This patent

From the US filing history. Foreign family members aren’t listed.

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