PERIPHERAL COMPONENT INTERCONNECT (PCI) BACKPLANE CONNECTIVITY SYSTEM ON CHIP (SoC)

A method comprising:

• reading memory region configuration definitions for memory regions, by a processor, wherein each memory region configuration definition identifies a size of a memory region, identifies a device where the memory region is located, and identifies another device allowed access to the memory region;
• for each device allowed access to one of the memory regions, writing the size of the memory region, by the processor, in a base address register (BAR) of a function circuit of an interface circuit coupled to the device, wherein each device is coupled to a different interface circuit;
• for each device having one of the memory regions, configuring a translation register of an output address translation unit (ATU) in the interface circuit coupled to the device by the processor with a local address;
• and
• for each device allowed access to one of the memory regions, configuring a translation register of an input ATU in the function circuit of the interface circuit coupled to the device by the processor with the local address, wherein the translation register of the input ATU is associated with the BAR of the function circuit of the interface circuit.

A method, comprising:

• receiving, by a first function circuit associated with a first circuit, a first transaction directed to a second circuit, wherein the first transaction includes a first address;
• determining, by the first function circuit, a local address based on the first address, a first plurality of registers and a first input address translation unit;
• and
• transmitting, by the first function circuit, the first transaction with the local address to the second circuit;
• and
• receiving, by an output address translation unit of the second circuit, the first transaction.