Facilitating sequential reads in memory sub-systems
AssigneeMicron Technology, Inc.
InventorsStephen Hanna, Nadav Grosz
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsStephen Hanna, Nadav Grosz
Estimating the term…
An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.
A system comprising:
A non-transitory computer-readable storage medium comprising executable instructions which, when executed by a processing device of a controller, cause the processing device to perform operations, comprising:
A non-transitory computer-readable storage medium comprising executable instructions which, when executed by a processing device of a host system, cause the processing device to perform operations, comprising:
Dependencies are inferred from the claim text.